对于用HDF旁路的HSP43220

对于用HDF旁路的HSP43220
TM
Using the HDF Bypass of the HSP43220

May 1998 TB312.1



When operated in the High Decimating Filter (HDF) bypass Clock Pulse Width High -
mode, the HSP43220 Decimating Digital Filter (DDF)
tSPWH . . . . . . . . . . . . . . . . . . 13ns minimum
requires clock timing relationships that are different from the
normal operation congurations. Clock Skew Between CK_IN and FIR_CLK -