无需板仿真即可估计实际的输出时序

无需板仿真即可估计实际的输出时序
White Paper: Xilinx FPGAs

R




WP217 (v1.0) December 23, 2004



Estimating Actual Output Timing
Without Board Simulation
By: Tim Blanchard and Michael Margolese




This document can help designers obtain more
accurate I/O timing data without the need for board-
level IBIS or SPICE simulations. Until recently, Xilinx
specified outputs into a lumped capacitive load.