在 Spartan-3A FPGA 内实现 DDR2-400 存储器接口

在 Spartan-3A FPGA 内实现 DDR2-400 存储器接口
Application Note: Spartan-3A FPGA Family

R Implementing DDR2-400 Memory Interfaces
in Spartan-3A FPGAs
Author: Eric Crabill
XAPP458 (v1.0) September 19, 2007


Summary High-performance consumer products and their requirement for low-cost, high-bandwidth
memory create demand for high-performance DDR2 memory interfaces. Xilinx offers a
Memory Interface Generator (MIG) integrated in the CORE Gen