10 Gigabit Ethernet/Fibre Channel PCS Reference Design - Not Recommended for New Designs

10 Gigabit Ethernet/Fibre Channel PCS Reference Design - Not Recommended for New Designs
Product Not Recommended for New Designs
Application Note: Virtex-II/Virtex-II Pro

R 10 Gigabit Ethernet/FibreChannel PCS
Reference Design
XAPP775 (v1.0) August 25, 2004 Author: Justin Gaither and Marc Cimadevilla



Summary This application note describes the 10 Gigabit Ethernet Physical Coding Sublayer (PCS)
reference design for Xilinx Virtex-II and Virtex-II Pro FPGAs. The PCS connects between