【应用手册】Power Optimization in Stratix III FPGAs

【应用手册】Power Optimization in Stratix III FPGAs
The Stratix® III family of devices from Altera® is based on 65-nm
technology and uses the most advanced architecture and power saving
techniques. These power saving techniques cover a variety of process,
circuit, and architecture optimizations and innovations. Stratix III devices
are based on a 1.1 V core voltage, triple-gate oxide, all-copper routing
65-nm process technology with low-k dielectric material that
dramatically reduces power and improves performance. Stratix III
devices include advanced, efficient logic structures called adaptive logic
modules (ALMs) that obtain maximum performance while minimizing
power consumption.
Altera provides the Quartus® II PowerPlay Power Analyzer tool to aid
you during the design process by delivering fast and accurate estimations
of power consumption. You can use this information to locate the blocks
in your design that are consuming the most power and target those blocks
to minimize the power consumption of your design.
Power Optimization in
Stratix III FPGAs

August 2007, ver. 2.0 Application Note 437



Introduction The Stratix III family of devices from Altera is based on 65-nm
technology and uses the most advanced architecture and power saving
techniques. These power saving techniques cover a variety of process,
circuit, and architecture optimizations and innovations. Stratix III devices
are based on a 1.1 V core voltage, triple-gate oxide, all-copper routing
65-nm process technology with low-k d