IEEE Standard for SystemVerilog_2005

IEEE Standard for SystemVerilog_2005
IEEE Standard for SystemVerilog―
Unified Hardware Design, Specification,
and Verification Language



IEEE Computer Society
Sponsored by the
Design Automation Standards Committee
and the
IEEE Standards Association Corporate Advisory Group




IEEE
3 Park Avenue IEEE Std 1800-2005
New York, NY 10016-5997, USA

22 November 2005




Authorized licensed use limited to: XIDIAN UNIVERSITY. Downloaded on July 31,2011 at 02:45:48 UTC from IEEE Xplore. Restrictions apply.
Authorized licensed use limited to: XIDIAN UNIVERSITY. Downloaded on July 31,2011 at 02:45:48