e-c8051f018_9.pdf

e-c8051f018_9.pdf
PRELIMINARY C8051F018
C8051F019
Mixed-Signal 16KB ISP FLASH MCU Family
ANALOG PERIPHERALS HIGH SPEED 8051 C CORE
- SAR ADC - Pipelined Instruction Architecture; Executes 70% of
§ 10-bit Instruction Set in 1 or 2 System Clocks
§ ±1LSB INL; No Missing Codes - Up to 25MIPS Throughput with 25MHz Clock
§ Progra