Paper_A:
1）full_case parallel_case_, the Evil Twins of Verilog Synthesis;
2）A Proposal To Remove Those Ugly Register Data Types From Verilog；
3）Asynchronous Synchronous Reset；
4）Coding And Scripting Techniques For FSM Designs With Synthesis-Optimized,Glitch-Free Outputs；
5）Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!；
6）RTL Coding Styles That Yield Simulation and Synthesis Mismatches；
Paper_B:
7）Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons；
8）State Machine Coding Styles for Synthesis；
9）Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs；
10）SystemVerilog - Is This The Merging of Verilog VHDL；
11）Verilog Coding Styles For Improved Simulation Efficiency；
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