Finite state machines are widely used in digital circuit designs. Generally, when designing a state machine using an HDL, the synthesis tools will optimize away all states that cannot be reached and generate a highly optimized circuit. Sometimes, however, the optimization is not acceptable. For example, if the circuit powers up in an invalid state, or the circuit is in an extreme working environment and a glitch sends it into an undesired state, the circuit may never get back to its normal operating condition.
This paper discuses a general methodology when creating a state machine using the HDL Designer SeriesTM State Diagram Editor. You can specify the design so that synthesis tools will not optimize away those unused states, thus a “safe” state machine can be generated.
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