The Ten Commandments of Excellent Design―VHDL Code Examples
Just in case you forgot, here are the Ten Commandments of Excellent Design:
1. All state machine outputs shall always be registered
2. Thou shalt use registers, never latches
3. Thy state machine inputs, including resets, shall be synchronous
4. Beware fast paths lest they bite thine ankles
5. Minimize skew of thine clocks
6. Cross clock domains with the greatest of caution. Synchronize thy signals!
7. Have no dead states in thy state machines
8. Have no logic with unbroken asynchronous feedback lest the fleas of
myriad Test Engineers infest thee
9. All decode logic must be crafted carefully―eschew asynchronicity
10. Trust not thy simulator―it may beguile thee when thy design is jun
我要上传