TABLE OF CONTENTS
CHAPTER 1 INTRODUCTION .................................................................................1
1.1 Motivation ..........................................................................................................1
1.2 Organization of the Dissertation ........................................................................1
1.3 ADC Definition..................................................................................................2
1.4 ADC Characterization........................................................................................4
1.4.1 Resolution ..............................................................................................4
1.4.1.1 Nonlinearity5
1.4.1.2 Signal to Noise Ratio6
1.4.1.3 Signal to Noise + Distortion Ratio7
1.4.1.4 Dynamic Range8
1.4.1.5 Spurious Free Dynamic Range8
1.4.2 Sampling Rate........................................................................................9
1.4.3 Input Bandwidth.....................................................................................9
1.4.4 Power Supply Rejection Ratio .............................................................10
1.4.5 Input Capacitance.................................................................................10
1.4.6 Input Signal Swing...............................................................................10
1.4.7 Power Dissipation ................................................................................10
CHAPTER 2 REVIEW OF ANALOG TO DIGITAL CONVERTER
ARCHITECTURES.............................................................................12
2.1 Flash ADC .......................................................................................................12
2.2 Two Step Flash ADC .......................................................................................14
2.3 Subranging ADC..............................................................................................16
2.4 Successive Approximation ADC .....................................................................17
2.5 Pipelined ADC.................................................................................................19
2.6 Recirculating ADC...........................................................................................21
2.7 Oversampled ADC...........................................................................................22
2.8 Serial ADC.......................................................................................................23
2.9 Recent Performance Achievements .................................................................24
CHAPTER 3 DESIGN TECHNIQUES FOR PIPELINED ANALOG
TO DIGITAL CONVERTERS ............................................................43
3.1 Introduction to the Concept of Pipelined ADCs .............................................43
3.2 Switched Capacitor DAC and Residue Amplifier............................................47
3.3 Sources of Error in Pipelined Analog to Digital Converters............................51
vii
3.3.1 Thermal Noise......................................................................................51
3.3.2 Comparator Offsets..............................................................................52
3.3.3 Residue Amplifier Gain Error..............................................................56
3.3.4 Nonuniform Reference Levels (Nonlinear DAC)...............................61
3.3.5 Residue Amplifier Nonlinearity...........................................................68
3.3.6 Incomplete Settling of the Sample and Hold Amplifier Output ..........78
3.3.6.1 Settling Time of a Single Pole System79
3.3.6.2 Settling Time of a Critically Damped Two Pole System79
3.3.6.3 Settling Time of an Underdamped Two Pole
System80
3.3.6.4 Settling Time of an Overdamped Two Pole System83
3.3.6.5 Tabulated Settling Times85
3.3.7 Sample and Hold Tracking Nonlinearity .............................................86
3.4 Error Correction Techniques............................................................................98
3.4.1 Analog Offset Correction.....................................................................98
3.4.2 Digital Comparator Error Correction.................................................103
3.4.3 Analog DAC/Gain Calibration ..........................................................107
3.4.4 Capacitor Error Averaging.................................................................110
3.4.5 Digital DAC/Gain Calibration ...........................................................113
CHAPTER 4 SAMPLE AND HOLD AMPLIFIER ARCHITECTURES
AND OPTIMIZATION......................................................................123
4.1 MOSFET Models for Transient Analysis .....................................................123
4.1.1 Long Channel Model for the MOSFET.............................................124
4.1.2 Vertical Field Mobility Degradation..................................................125
4.1.3 Velocity Saturation ............................................................................126
4.1.4 Subthreshold ......................................................................................130
4.1.5 Putting the Models Together..............................................................130
4.2 Settling Time Analysis of Switched Capacitor Gain Stages..........................134
4.2.1 Single Stage Single Pole Amplifier ...................................................137
4.2.1.1 Fixed Current Density139
4.2.1.1.1 Minimum Power with Fixed Speed141
4.2.2 Telescopic Cascode Amplifier...........................................................144
4.2.2.1 Optimization of Current Density to Minimize Power -
Fixed Speed and Fixed Feedback Capacitance - Model
Including Mobility Degradation, Velocity Saturation,
viii
and Subthreshold149
4.2.3 Wide-Band Preamplifier Driving a Single Stage Amplifier ..............155
4.2.3.1 Optimization to Minimize the Power161
4.2.4 Two Stage Amplifier with Standard Miller Compensation ...............167
4.2.5 Two Stage Amplifier with Ahuja Style Compensation .....................175
4.2.6 Three Stage Amplifier with Nested Miller Compensation ................187
4.2.7 Comparison of Topologies.................................................................198
Appendix.................................................................................................................203
4.A.1 Single Stage Amplifier Optimizations ........................................................205
4.A.1.1 Minimum Power with Fixed Speed ................................................206
4.A.1.2 Maximum Speed with Fixed Feedback Capacitance......................209
4.A.1.3 Speed and Power Optimization with Variable Current Density-Long
Channel Model...................................................................................211
4.A.1.3.1 Speed and Power Optimization with Variable Feedback
Capacitance214
4.A.1.3.2 Special Case: No Output Parasitic Capacitance219
4.A.2 Telescopic Cascode Amplifier Optimizations.............................................220
4.A.2.1 Optimization of Feedback Capacitance to Minimize Power - Fixed
Current Density and Speed ................................................................221
4.A.2.1.1 Results of Optimization Using the Long Channel
Model221
CHAPTER 5 OPTIMIZATION TECHNIQUES FOR PIPELINED
ANALOG TO DIGITAL CONVERTERS.........................................227
5.1 Pipelined Analog to Digital Converter Design in the Absence of Noise.......227
5.1.1 Optimum Sampling Capacitor Size to Minimize Pipeline Power .....227
5.1.2 Optimum Number of Bits Per Stage to Minimize Pipeline Power ....236
5.2 Pipelined Analog to Digital Converter Design in the Presence of Noise ......239
5.2.1 Thermal Noise in Switched Capacitor Gain Blocks ..........................241
5.2.1.1 Thermal Noise Contribution of the Sampling Switches
(kT/C Noise)241
5.2.1.2 Thermal Noise Contribution of the Transconductance
Amplifier243
5.2.1.2.1 Thermal Noise of a Single Stage
Amplifier244
5.2.1.2.2 Thermal Noise of a Critically Damped
Telescopic Cascode Amplifier247
5.2.1.2.3 Thermal Noise of a Preamplifier
ix
Driving a Single Stage Amplifier248
5.2.1.2.4 Thermal Noise of a Two Stage Miller
Compensated Amplifier251
5.2.1.2.5 Thermal Noise of an Amplifier with Ahuja
Style Compensation254
5.2.2 Optimal Capacitor Sizing in High Resolution-Low Speed Pipelined
Analog to Digital Converters .............................................................256
5.2.3 Optimal Closed Loop Gain of Interstage Gain Amplifiers in High Resolution-
High Speed Pipelined Analog to Digital Converters ............264
5.2.4 Optimum Closed Loop Gain of Interstage Gain Amplifiers in a Pipelined
ADC with Parasitics Included...................................................273
5.2.5 Optimum Supply Voltage for Power Dissipation in a Pipelined
ADC...................................................................................................280
5.2.5.1 Thermal Noise Limits to Power Dissipation in a Pipelined
ADC281
5.2.5.2 Power Dissipation Trade-offs in Choosing the Supply
Voltage283
5.3 Scaling of Power and Speed in an Optimized Pipelined ADC ......................289
Appendix.................................................................................................................295
CHAPTER 6 PROTOTYPE DESIGN AND DESCRIPTION.................................317
6.1 Design Goal ...................................................................................................317
6.2 Architecture....................................................................................................317
6.2.1 Comparator Architecture ...................................................................317
6.2.2 Encoding Network .............................................................................323
6.2.2.1 Voting Error Correction323
6.2.2.2 Digital to Analog Converter324
6.2.3 Sample and Hold Amplifier Architecture ..........................................332
6.2.4 Operational Amplifier Architecture...................................................334
6.2.5 Bias Circuit for the Operational Amplifier ........................................336
6.2.6 Clock Generation ...............................................................................341
6.2.7 Layout Considerations .......................................................................344
6.2.7.1 Sampling Capacitor Layout344
6.2.7.2 Interconnect Layout346
6.3 Power Supply Noise Issues ............................................................................348
CHAPTER 7 EXPERIMENTAL RESULTS ...........................................................357
7.1 Die Photograph ..............................................................................................357
7.2 Code Density Test ..........................................................................................358
x
7.3 Signal to Noise Ratio and Distortion .............................................................363
7.3.1 Results for Low Input Frequency (100kHz) ......................................364
7.3.2 Results for High Input Frequency (2MHz)........................................365
7.3.3 Signal to Noise Ratio Versus Input Amplitude..................................366
7.3.4 Idle Channel Noise.............................................................................368
7.4 Summary of Results.......................................................................................368
CHAPTER 8 CONCLUSIONS AND FUTURE WORK........................................371
8.1 Conclusions....................................................................................................371
8.1.1 Optimization of Pipelined ADCs .......................................................371
8.1.2 Opamp Architectures for Switched Capacitor Applications..............373
8.2 Pipelined ADC with Low Swing Amplifiers and Extra Comparators ..........374
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