资料介绍
Virtex-4 FPGAs deliver the industry’s best signal integrity, allowing you to pre-empt board issues at the chip level, for high-speed designs such as memory interfaces.Featuring a unique SparseChevron™ pin out pattern, the Virtex-4 family provides the highest ratio of VCCO/GND pins to user I/O pins available in any FPGA. By strategically positioning one hard power/ground pin adjacent to every user I/O on the device, we’ve reduced signal path inductance and SSO noise to levels far below
what you can attain with a virtual ground or soft ground architecture.
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