资料介绍
Although the Synopsys Design Compiler tool does an excellent job
of converting HDL to gates, the structure of the HDL may not allow
Design Compiler to meet the designer-specified constraints and is
very likely to result in an increase in compile time. The startpoint for
synthesis affects the quality of results after synthesis. Designersmust
keep performance requirements in mind and think in terms of
hardware, not software, when writing HDL.
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