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RTL Design Style Guide for Verilog - V1Chapter 3 RTL Design Methodology

Chapter 3 RTL Design Methodology

This chapter introduces the methodology for creating function libraries, the parameterization of design resources, test facilitation design, low power consumption design, and methods for managing design data. This chapter also introduces the methodology for improving design quality and the reusability of design resources.

3.1 Create function libraries

Contents

3.2 Using function libraries 3.3 Design for Test (DFT) 3.4 Low Power-Consumption Design 3.5 Source codes and design data management

3-1

3.1. Create function libraries

3.1. Create function libraries
3.1.1. Create and utilize function libraries
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Chapter 3 RTL Design Methodology

Create sub-programs which can be used in common Create reusable component librari