Xilinx spartant6 核心板原理图

spartan6 core boare5

4

3

2

1

Spartan6 Core Board
D

SDRAM
CAS RAS CLK WE BA A D
D

FPGA
SDRAM IF A[21:0] D[15:0] EN RW

USB DATA

IF

Video CLK Serial CLK
C

IFCLK D[15:0] FIFO FD[7:0] SLWR SLCS
C

LVDS INPUT

Serial To Parallel CCI656 Decode

Video DAT[7:0] Video Vsync Video Hsync FIFO

D[15:0]

Serial DAT

State Machine

Control

LVDS_Serial Clock

Main Clock

USB
WR RD

PC
B

B

Video CLK Serial CLK Parallel To Serial LVDS OUTPUT Serial DAT CCI656 Encode Video DAT[7:0] Video Vsync Video Hsync Video Generator DCM USB MCU IF

CD D[7:0]

A

Sys_clk

50M OSC

LED

EXT1,EXT2

A

5

4

3

2

1

5

4

3

2

1

D5V

POWER
D

USER_AUX
D5V D3.3V D1.2V D1.2V D3.3V D5V D3.3V

FPGA_CONFIG
D

D3.3V D1.2V

LVDS_DAT_O_N

LVDS_DAT_O_P

LVDS_CLK_O_N

LVDS_CLK_O_P

LVDS_DAT_I_N

USER_LED[0:3]

LVDS_DAT_I_P

LVDS_CLK_I