资料介绍
IEEE Standard for SystemVerilog_2005 IEEE Standard for SystemVerilog―
Unified Hardware Design, Specification,
and Verification Language
IEEE Computer Society
Sponsored by the
Design Automation Standards Committee
and the
IEEE Standards Association Corporate Advisory Group
IEEE
3 Park Avenue IEEE Std 1800-2005
New York, NY 10016-5997, USA
22 November 2005
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