5282系统设计与外设接口-part1

5282系统设计与外设接口-part1
嵌入式系统硬件接口设计


曾 嵘
2004.11
Coldfire MCF-5282
V2 ColdFire core delivering 76 (Dhrystone 2.1) MIPS at 80 MHz
running from Cache/RAM
512KB embedded flash memory
Enhanced Multiply-Accumulate Unit (eMAC) for DSP
functionality
64 Kbytes of static RAM
10/100 Ethernet MAC
Cache for external access support
Address decode and chip selects
CAN 2.0B controller area network interface with 16 message
buffers
Three UARTs with DMA capability
Queued serial peripheral interface (QSPI) with four peripheral
chip selects
8-channel 10-bit queued analog-to-digital converter (QADC)
Four 32-bit timers with capture, compare and DMA capability
Eight 16-bit timer channels for capture, compare, and pulse width
modulation
Four periodic interrupt timers (PITs)
I2C bus controller
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