TI CALYPSO platform architectu...

TI CALYPSO platform detail designCALYPSO - Overview

CALYPSO OVERVIEW
Henry chen
Texas Instruments Shanghai Wireless Customer Intergration & Design Center

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Calypso General Description

GPRS class 12 capability; Full-Rate, Enhanced Full-Rate and HalfRate speech coding capability 2 Processor Cores: ARM7TDMIE: 0~39MHz DSP TMS320C54x: 0~91MHz 179-PIN
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Calypso ARM Block Overview (1)

General purpose peripherals: ・ 4 M-bit (512K-byte) SRAM ・ ARM Memory Interface for External RAM & Flash ・ MPU (Memory Protection Unit):512K-byte
for 4 regions

・ Debug Unit (DU)

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Calypso ARM Block Overview (2)

Application peripherals: ・ GPIO: Keyboard & 2 PWM (Light, Buzzer) ・ UWIRE(3.25MHz)/I2C(100/400KHz): LCD/EPROM ・ 3 Timers: 2 General, 1 Watchdog ・ UART_IRDA: Debug (Max 115.2k baudrate) ・ UART_MODEM: (Max 115