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i80接口时序i80 时序逻辑硬件描述
1、VHDL 代码描述 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity RGBDATA is port( RGBDATA: in std_logic_vector(15 downto 0); LCDDATA: out std_logic_vector(15 downto 0); CLK: in std_logic; RST: in std_logic; RS: out std_logic; CS: out std_logic; WR: out std_logic; RD: out std_logic); end; architecture behav of RGBDATA is signal LATCH_DATA:std_logic_vector(15 downto 0); signal state:std_logic_vector(4 downto 0); --state(3)=RS;state(2)=CS;state(1)=WR;state(0)=RD; constant state0: std_logic_vector(4 downto 0) :="01111";--init select constant state1: std_logic_vector(4 downto 0) :="01011";--chip select constant state2: std_logic_vector(4 downto 0) :="01001";--wr is low constant state3: std_logic_vector(4 downto 0) :="11011";--wr is high begin moore:pr
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