基于直接数字综合的 E1/T1 的时钟数据恢复设计技巧

基于直接数字综合的 E1/T1 的时钟数据恢复设计技巧
Application Note: Virtex and Spartan FPGA Families

R Clock Data Recovery Design Techniques for
E1/T1 Based on Direct Digital Synthesis
Author: Paolo Novellini and Giovanni Guasti
XAPP868 (v1.0) January 29, 2008


Summary Low data rates (less than 10 Mb/s) in a telecommunications environment can be terminated
and regenerated by fully digital PLLs in today’s Xilinx FPGAs. In a direct digital synthesis (DDS)
b