ISLA11xP50输出数据的时间和同步

ISLA11xP50 Output Data Timing and Synchronization
Application Note 1604


ISLA11xP50 Output Data Timing and Synchronization
Overview This document is intended to provide basic guidance on
the ISLA11xP50’s output timing and synchronization
Capturing data from the ISLA11xP50 ADC is easily
methods.
accomplished with current FPGA technology. The
source-synchronous LVDS interface provides DDR output
data at up to 500MHz with a 250MHz clock. The clock and
Output Timing
data are aligned within ±250ps providing a wide