资料介绍
Conventional charge pump circuits use a fixed
switching frequency that leads to power efficiency degradation
for loading less than the rated loading. This paper proposes a
level shifter design that also functions as a frequency converter
to automatically vary the switching frequency of a dual charge
pump circuit according to the loading. The switching frequency is
designed to be 25 kHz with 12 mA loading on both inverting and
noninverting outputs. The switching frequency is automatically
reduced when loading is lighter to improve the power efficiency.
The frequency tuning range of this circuit is designed to be
from 100 Hz to 25 kHz. A start-up circuit is included to ensure
proper pumping action and avoid latch-up during power-up. A
slow turn-on, fast turn-off driving scheme is used in the clock
buffer to reduce power dissipation. The new dual charge pump
circuit was fabricated in a 3-m p-well double-poly single-metal
CMOS technology with breakdown voltage of 18 V, the die size
is 4.7 4.5 mm2
. For comparison, a charge pump circuit with
conventional level shifter and clock buffer was also fabricated.
The measured results show that the new charge pump has two
advantages: 1) the power dissipation of the charge pump is
improved by a factor of 32 at no load and by 2% at rated
loading of 500
and 2) the breakdown voltage requirement
is reduced from 19.2 to 17 V852 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 6, JUNE 1997
Efciency Improvement in Charge Pump Circuits
Chi-Chang Wang and Jiin-chuan Wu
Abstract― Conventional charge pump circuits use a xed ventional charge pump circuits are designed to operate at a
switching frequency that leads to power efciency degradation xed switching frequency with a rated output load current
for loading less than the rated loading. This paper proposes a and voltage. For a CMOS charge pump circuit with a given
level shifter design that also functions as a frequency converter
to automatically vary the switching frequency of a du
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