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Verilog开发的能下载到FPGA实验板上运行的多周期CPU

资料介绍
lab8\.lso
....\12.v
....\alu.v
....\alu_wrapper.v
....\anti_jitter.v
....\ctrl.v
....\ctrl.v.bak
....\device_usage_statistics.html
....\dis32bits.prj
....\dis32bits.stx
....\dis32bits.v
....\dis32bits.xst
....\lab8.ise
....\lab8.ntrc_log
....\lab8.restore
....\...._xdb\cst.xbcd
....\........\tmp\ise\version
....\........\...\...\__OBJSTORE__\HierarchicalDesign\HDProject\HDProject
....\........\...\...\............\..................\.........\HDProject_StrTbl
....\........\...\...\............\..................\__stored_object_table__
....\........\...\...\............\PnAutoRun\Scripts\RunOnce_tcl
....\........\...\...\............\.........\.......\RunOnce_tcl_StrTbl
....\........\...\...\............\.rojectNavigator\dpm_project_main\dpm_project_main
....\........\...\...\............\................\................\dpm_project_main_StrTbl
....\........\...\...\............\................\................\NameMap
....\........\...\...\............\................\................\NameMap_StrTbl
....\........\...\...\............\................\__stored_objects__
....\........\...\...\............\................\__stored_objects___StrTbl
....\........\...\...\............\................\__stored_object_table__
....\........\...\...\............\................Gui\GuiProjectData
....\........\...\...\............\...................\GuiProjectData_StrTbl
....\........\...\...\............\xreport\Gc_RvReportViewer-Current-Module
....\........\...\...\............\.......\Gc_RvReportViewer-Current-Module_StrTbl
....\........\...\...\............\.......\Gc_RvReportViewer-Module-Data-top
....\........\...\...\............\.......\Gc_RvReportViewer-Module-Data-top_StrTbl
....\........\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default
....\........\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default_StrTbl
....\........\...\...\..REGISTRY__\Autonym\regkeys
....\........\...\...\............\bitgen\regkeys
....\........\...\...\............\common\regkeys
....\........\...\...\............\.pldfit\regkeys
....\........\...\...\............\Cs\regkeys
....\........\...\...\............\dumpngdio\regkeys
....\........\...\...\............\ExpandedNetlistEngine\regkeys
....\........\...\...\............\fuse\regkeys
....\........\...\...\............\HierarchicalDesign\HDProject\regkeys
....\........\...\...\............\..................\regkeys
....\........\...\...\............\hprep6\regkeys
....\........\...\...\............\idem\regkeys
....\........\...\...\............\map\regkeys
....\........\...\...\............\netgen\regkeys
....\........\...\...\............\.gc2edif\regkeys
....\........\...\...\............\...build\regkeys
....\........\...\...\............\..dbuild\regkeys
....\........\...\...\............\par\regkeys
....\........\...\...\............\ProjectNavigator\regkeys
....\........\...\...\............\................Gui\regkeys
....\........\...\...\............\runner\regkeys
....\........\...\...\............\SrcCtrl\regkeys
....\........\...\...\............\.TE\bitgen\regkeys
....\........\...\...\............\...\map\regkeys
....\........\...\...\............\...\ngdbuild\regkeys
....\........\...\...\............\...\par\regkeys
....\........\...\...\............\...\regkeys
....\........\...\...\............\...\trce\regkeys
....\........\...\...\............\...\xst\regkeys
....\........\...\...\............\taengine\regkeys
....\........\...\...\............\.rce\regkeys
....\........\...\...\............\.sim\regkeys
....\........\...\...\............\vhpcomp\regkeys
....\........\...\...\............\.logcomp\regkeys
....\........\...\...\............\WebTalk\DesignDataCollection\regkeys
....\........\...\...\............\.......\regkeys
....\........\...\...\............\xpwr\regkeys
....\........\...\...\............\.report\regkeys
....\........\...\...\............\XSLTProcess\regkeys
....\........\...\...\............\xst\regkeys
....\........\...\...\............\_ProjRepoInternal_\regkeys
....\........\...\ise.lock
....\memory.asy
....\memory.coe
....\memory.mif
....\memory.ngc
....\memory.sym
....\memory.v
....\memory.veo
....\memory.vhd
....\memory.vho
....\memory.xco
....\memory11a.coe
....\memory11b.coe
....\memory_flist.txt
....\memory_readme.txt
....\memory_xmdf.tcl
....\regs.v
....\reg_wrapper.v
....\templates\coregen.xml
....\test.txt
....\timer_500ms.v
....\top.bgn
标签:FPGA资源Xilinx
Verilog开发的能下载到FPGA实验板上运行的多周期CPU
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