下面是我的epp代码，很简单，通过pc机程序控制led亮和灭。附件有份并口资料和我自己的一点总结及本代码的状态机
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:57:05 10/24/05
// Design Name:
// Module Name: EPP_and_LED
// Project Name:
// Target Device:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module EPP_and_LED(Write, Data,Interrupt, Wait, DataStrobe, Reset, AddressStrobe,rst,led,clk/*,t1,t2,t3,t4*/);
input Write;
inout [7:0] Data;
output Interrupt;
output Wait;
input DataStrobe;
input Reset;
input AddressStrobe;
wire [7:0] Data;
/* output t1,t2,t3,t4; //测试信号,用于map到测试用的跳线
wire t1,t2,t3,t4; */
input clk;//input clock 24M
reg Wait,Interrupt;
input rst;//reset switch ,reference PCB,active low
output led;//led control,1 to switch led on
reg led;
parameter Idle=3'b000, Wait_End_AddrWrite=3'b001, Wait_End_AddrRead=3'b010,
Wait_End_DataWrite=3'b011, Wait_End_DataRead=3'b100;
//EPP state machine,reference EPP specification
//internal reg
reg [2:0] state;
reg [7:0] addr; //用于存储EPP地址写
reg [7:0] datain;//用于存储EPP数据写
reg [7:0] dataout; //用于向EPP Data 输出,可以是数据或者地址
always @ (posedge clk)
if((!rst)|| (!Reset)) //on PCB rst or Rest from EPP
begin
state=Idle;
addr=0;
datain=0;
dataout=0;
led=1;
Wait=0;
Interrupt=0;
end
else //state machine
begin
led=datain[0];
case(state)
Idle: begin
Wait=0;
state=Idle;
if(AddressStrobe==0)
begin
if(Write==1)
begin
//put address in Data bus here
dataout=8'b1011_1111;
Wait=1;
state=Wait_End_AddrRead;
end
else if(Write==0)
begin
addr=Data;
Wait=1;
state=Wait_End_AddrWrite;
end
end
else if(DataStrobe==0)
begin
if(Write==1)
begin
//put data in Data bus here
dataout=8'b1111_1011;
Wait=1;
state=Wait_End_DataRead;
end
else if(Write==0)
begin
datain=Data;
Wait=1;
state=Wait_End_DataWrite;
end
end
end
Wait_End_AddrRead:begin
if(AddressStrobe==1)
begin
Wait=0;
state=Idle;
end
end
Wait_End_AddrWrite:begin
if(AddressStrobe==1)
begin
Wait=0;
state=Idle;
end
end
Wait_End_DataRead:begin
if(DataStrobe==1)
begin
Wait=0;
state=Idle;
end
end
Wait_End_DataWrite:begin
if(DataStrobe==1)
begin
Wait=0;
state=Idle;
end
end
default: state=Idle;
endcase
end
assign Data[7:0]=((state==Wait_End_DataRead)||(state==Wait_End_AddrRead))? dataout[7:0]:8'bz;
/*assign t1=Write;
assign t2=DataStrobe;
assign t3=Wait;
assign t4=dataout[0]; */
endmodule |
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