《时间触发嵌入式系统设计模式 8051系列微控制器开发可靠应用》

《时间触发嵌入式系统设计模式 8051系列微控制器开发可靠应用》
RapidiTTy FPGA
RapidiTTy FPGA includes the full source-code for
the PH 03 Core, which is a full 32-bit processor core
based on the MIPS I Instruction Set Architecture
(excluding patented instructions). It includes the
following peripherals:
JTAG Debugging.
16-bit Timer.
Buffered UART.
These peripherals are connected to the processor
core through the use of a dedicated bus, which can
be used to expand the functionality of the PH Core.



RapidiTTy Builder
RapidiTTy Builder ships with library code covering
many common embedded tasks, including reading from
switc