（最高质量）DATACONVERTERSFORWIRELESSSTANDARDS

（最高质量）DATA CONVERTERS FOR WIRELESS STANDARDS

CHUNLEI SRI
Qualcomm COMA Technologies
Qualcomm Inc.
San Diego, CA 92121, USA


MOHAMMED ISMAIL
Analog VLSllab.
The Ohio State University
Columbus, OH 43210, USA
KLUWER

@2002 Kluwer Academic Publishers

Contents
List of Figures ix
List of Tables xiii
Preface xv
1. INTRODUCTION 1
1 Background 1
2 Motivation and Goals 4

2. OVERVIEW OF WIRELESS RECEIVER ARCHITECTURES 7
1 Introduction 7
2 Receiver Architecture 7
2.1 Superheterodyne Architecture 8
2.2 Zero-IF Architecture 9
2.3 Low-IF Architecture 10
2.4 Wideband IF Double Conversion Architecture 10

3 Multi-standard Receiver Architecture 12
3. LOW POWER ADC DESIGN 15
1 Introduction 15
2 Characterizations of ADC 15
3 Review of ADC Architectures 17
3.1 Flash ADC 17
3.2 Interpolating and Folding ADC 17
3.3 Two-Step ADC 19
3.4 Oversampling ADC 19
3.5 Pipeline ADC 20

4 Overview of Pipeline ADC Designs 21
4.1 Key Building Blocks 21
4.1.1 Switched-Capacitor DAC and Residue Amplifier 22
4.1.2 Sub-ADC 22
4.1.3 Sample-and-Hold 23
4.2 Digital Error Correction 23
4.3 Design Considerations 26
4.3.1 Size of Capacitors 26
4.3.2 Capacitor Matching 27
4.3.3 Amplifier Architecture 28
4.3.4 Amplifier Requirements 28
4.3.5 Error Tolerances 31

5 Power Optimization Techniques 32
5.1 Optimizing the Stage Resolution 32
5.2 Dynamic Comparator 33
5.3 Capacitor/Amplifier Scaling 34
5.4 Dynamic Biasing 34
6 Summary 37
4. PROTOTYPE DESIGN: ADC FOR WLAN(DSSS)IWCDMA 39
1 Introduction 39
2 Applications 39
3 Architecture 40
4 High-Speed OTA 42
4.1 OTA Requirements 42
4.2 OTA Topology 43
4.2.1 DC Gain 44
4.2.2 Gain-Bandwidth 44
4.2.3 Slew Rate 44
4.2.4 Thermal Noise 45
4.3 CMFB 45
4.4 Results 45
5 Comparator 46
6 Clock Generator 47
7 Smart-Biasing Technique 49
8 Prototype Implementation 49
9 Performance of the Prototype ADC 49
10 Summary 50

5. DESIGN CONSIDERATIONS OF LOW VOLTAGE ADCS 53
1 Introduction 53
2 Challenges in Low Voltage ADC Design 54
2.1 Low Voltage CMOS Switches 56
3 Low-FT Devices 58
4 Clock Boosting 59
5 Switched-Opamp 60
6 A Modified Switched-opamp Technique 62
6.1 Input Stage 62
6.2 High Speed Design Techniques 66
7 Summary 68
6. ADC FOR BLUETOOTHlWLAN(FHSS)IHOMERF 71
1 Applications 71
2 System Level Design 73
3 A Switched-opamp MDAC 74
4 Opamp Design 75
4.1 DC Gain 76
4.2 Frequency Response 77
4.3 Slew Rate 78
4.4 Noise 79
4.5 Common-Mode Feedback (CMFB) 80
5 Comparator Design 81
6 Clock Generator 83
7 Digital Correction Circuit 84
8 Performance 84
9 Summary 86

7. HIGH-RESOLUTION DAC DESIGN TECHNIQUES 91
1 Review of DAC Architectures 91
1.1 Current Steering DAC 91
1.2 Switched-Capacitor DAC 93
1.3 Resistor String DAC 94
2 Intrinsic Matching of Resistor-String DAC 94
2.1 Resistor Matching Model 95
Vlll DATA CONVERTERS FOR WIRELESS STANDARDS
2.2 Design Techniques for Improved Resistor Matching 97
2.2.1 Reducing Random Errors 97
2.2.2 Reducing Gradient Errors 99
3 Summary 101

8. CONTROL DAC FOR 3G (UMTS) TRANSCEIVERS 103
1 Applications 103
2 Design Specifications 104
3 Architecture 104
4 Design of Resistor Strings 107
5 Class-AB Output Buffer 108
6 Deglitching Circuit 110
7 Performance of the Prototype DAC 112
8 Summary 114

9. CONCLUSION 117
Index