Re-UsableLowPowerDSPIPembeddedinanARMbasedSoCArchitecture

The integration of different re-usable IPs (Intellectual Properties) to design SoC (System-on-Chip) devices is widely accepted as the key to achieving higher productivity to meet shorter time-to-market demands. Nevertheless, productivity improvements suffer because the importance of interface definitions and consequently the integration of IPs for the targeted SoC architecture is often treated as a secondary issue. This paper describes a scheme for the integration of a low power DSP IP embedded in an ARM based SoC architecture which is characterised by having two interfaces intended for two different types of on-chip bus configurations. A DSP IP has been implemented using this scheme. The power consumption of the actual FIR filtering algorithm realised within the DSP IP has been compared to a conventional implementation using an Alcatel 0.35 μm CMOS technology.