TMDSEVM6678LEVM技术参考手册版本2.01

TMDSEVM6678L EVM Technical Reference Manual Version 2.01

TMDSEVM6678L EVM 技术参考手册 版本2.01

Contents
1. Overview .............. 11
1.1 Key Features ............... 11
1.2 Functional Overview .................. 12
1.3 Basic Operation .................. 12
1.4 Boot Mode and Boot Configuration Switch Setting .......... 13
1.5 Power Supply ............. 14
2. Introduction to the TMDSEVM6678L board ........ 15
2.1 Memory Map ............. 15
2.2 EVM Boot Mode and Boot Configuration Switch Settings ........ 18
2.3 JTAG \ Emulation Overview ................ 18
2.4 Clock Domains ............ 19
2.5 I2C Boot EEPROM / SPI NOR Flash ............. 20
2.6 FPGA ................... 21
2.7 Gigabit Ethernet Connections ............ 22
2.8 Serial RapidIO (SRIO) Interface .......... 22
2.9 DDR3 External Memory Interface .............. 23
2.10 16\bit Asynchronous External Memory Interface (EMIF\16) ........... 23
2.11 HyperLink Interface .................. 24
2.12 PCIe Interface ................... 25
2.13 Telecom Serial Interface Port (TSIP) ........ 25
2.14 UART Interface ................. 26
2.15 Module Management Controller (MMC) for IPMI .......... 26
2.16 Expansion Header ............ 27
3. TMDSEVM6678L Board Physical Specifications ........... 28
3.1 Board Layout .............. 28
3.2 Connector Index ................. 29
3.2.1 560V2_PWR1, XDS560v2 Mezzanine Power Connector ...... 30
3.2.2 AMC1, AMC Edge Connector ............... 30
3.2.3 COM1, UART3 Pin Connector ............... 32
3.2.4 COM_SEL1, UART Route Select Connector .......... 32
3.2.5 DC_IN1, DC Power Input Jack Connector............. 33
3.2.6 EMU1, TI 60\Pin DSP JTAG Connector .......... 33
3.2.7 FAN1, FAN Connector ........... 34
3.2.8 HyperLink1, HyperLink Connector ....... 35
3.2.9 LAN1, Ethernet Connector ........... 37
3.2.10 PMBUS1, PMBUS Connector for Smart\Reflex Control ..... 37
3.2.11 TAP_FPGA1, FPGA JTAG Connector (For Factory Use Only) ....... 38
3.2.12 SBW_MMC1, MSP430 SpyBiWire Connector (For Factory Use Only) ....... 39
3.2.13 TEST_PH1, Expansion Header (EMIF\16, SPI, GPIO, Timer I/O, I2C, and
UART) ............... 39
3.2.14 USB1, Mini\USB Connector ........ 41
3.3 DIP and Pushbutton Switches ............ 41
3.3.1 RST_FULL1, Full Reset .......... 41
3.3.2 RST_COLD1, Cold Reset ................ 42
3.3.3 RST_WARM1, Warm Reset........... 42
3.3.4 SW3, SW4, SW5, and SW6, DSP boot mode and Configuration .. 42
3.3.4 SW9, DSP PCIESS Enable and User Defined Switch Configuration ...... 44
3.4 Test Points .................. 45
3.5 System LEDs ............... 47
4. System Power Requirements ............... 48
4.1 Power Requirements ................. 48
4.2 The Power Supply Distribution .......... 50
4.3 The Power Supply Boot Sequence ............. 54
5. TMDSEVM6678L FPGA FUNCTIONAL DESCRIPTION ............ 59
5.1 FPGA overview ................... 59
5.2 FPGA signals description ............ 60
5.3 Sequence of operation ............... 66
5.3.1 Power\On Sequence ................ 67
5.3.2 Power Off Sequence ................ 67
5.3.3 Boot Configuration Timing .............. 68
5.3.4 Boot Configuration Forced in I2C Boot ........... 69
5.4 Reset definition .................. 69
5.4.1 Reset Behavior ................ 69
5.4.2 Reset Switches and Triggers ............ 70
5.5 SPI protocol ................ 71
5.5.1 FPGA\DSP SPI Protocol ............ 71
5.5.2 FPGA\ CDCE62005(Clock Generator) SPI Protocol .......... 73
5.5.3 The FPGA\ programming CDCE62005 from the DSP ....... 74
5.5.4 CDCE62005 programming sequences on the FPGA ........ 76
5.5.5 CDCE62005 default value on the EVM ......... 77
5.6 FPGA Configuration Registers ............ 78
5.6.1 FPGA Configuration Registers Summary ......... 78
5.6.2 FPGA Configuration Registers Descriptions ............ 79
List of Figures
Figure 1.1: Block Diagram of TMDSEVM6678L EVM ....... 12
Figure 1.2: TMDSEVM6678L EVM Layout ................ 13
Figure 2.1: TMDSEVM6678L EVM JTAG emulation ......... 19
Figure 2.2: TMDSEVM6678L EVM Clock Domains ........... 20
Figure 2.3: TMDSEVM6678L EVM FPGA Connections ............. 21
Figure 2.4: TMDSEVM6678L EVM Ethernet Routing ....... 22
Figure 2.5: TMDSEVM6678L EVM SRIO Port Connections ...... 22
Figure 2.6: TMDSEVM6678L EVM SDRAM ............... 23
Figure 2.7: TMDSEVM6678L EVM EMIF\16 connections ......... 24
Figure 2.8: TMDSEVM6678L EVM HyperLink connections ...... 24
Figure 2.9: TMDSEVM6678L EVM PCIE Port Connections ....... 25
Figure 2.10: TMDSEVM6678L EVM TSIP connections ............. 26
Figure 2.11: TMDSEVM6678L EVM UART Connections ........... 26
Figure 2.12: TMDSEVM6678L EVM MMC Connections for IPMI ..... 27
Figure 3.1: TMDSEVM6678L EVM Board Assembly Layout C TOP view .......... 28
Figure 3.2: TMDSEVM6678L EVM Board layout C Bottom view ...... 29
Figure 3.3: COM_SEL1 Jumper setting ............. 33
Figure 3.4 : The HyperLink Connector ............. 35
Figure 3.5 : TAP_FPGA1 function diagram ............... 39
Figure 3.6 : SW3, SW4, SW5, and SW6 default settings .......... 42
Figure 3.7 : SW9 default settings ............. 44
Figure 3.8 : TMDSEVM6678L test points on top side .............. 45
Figure 3.9 : TMDSEVM6678L test points on the bottom side.......... 45
Figure 3.10 : TMDSEVM6678L EVM Board LEDs .............. 47
Figure 4.1: All the AMC power supply on TMDSEVM6678L EVM ............ 51
Figure 4.2: The CVDD and VCC1V0 (CVDD1) power design on TMDSEVM6678L EVM ... 52
Figure 4.3: The VCC3_AUX power design on TMDSEVM6678L EVM ...... 53
Figure 4.4: The VCC1V5 power design on TMDSEVM6678L EVM ........... 53
Figure 4.5: The VCC5 power design on TMDSEVM6678L EVM ....... 54
Figure 4.6: Initial Power Up Sequence Timing Diagram .......... 57
Figure 4.7: Initial Power Down Sequence Timing Diagram ............. 58
Figure 5.1: Power\On Reset Boot Configuration Timing .......... 68
Figure 5.2: Reset\Full Switch/Trigger Boot Configuration Timing ............ 69
Figure 5.3: The SPI access form the TMS320C6678 to the FPGA (WRITE / high level) .... 72
Figure 5.4: The SPI access form the TMS320C6678 to the FPGA (WRITE) ....... 72
Figure 5.5: The SPI access form the TMS320C6678 to the FPGA (READ / high level)...... 72
Figure 5.6: The SPI access form the TMS320C6678 to the FPGA (READ) ........ 73
Figure 5.7: The SPI access form the FPGA to the CDCE62005 (WRITE) ........... 73
Figure 5.8: The SPI access form the FPGA to the CDCE62005 (READ) ..... 73