完整的用VERILOG语言开发的USB2.0IP核源代码

详细说明：完整的用VERILOG语言开发的USB2.0 IP核源代码，包括文档、仿真文件.

文件列表:

USB2.0的IP核，包含文档和Verilog源码

...................................\usb_funct

...................................\.........\bench

...................................\.........\.....\CVS

...................................\.........\.....\verilog

...................................\.........\.....\.......\CVS

...................................\.........\doc

...................................\.........\...\CVS

...................................\.........\...\README.txt

...................................\.........\...\STATUS.txt

...................................\.........\...\usb_doc.pdf

...................................\.........\rtl

...................................\.........\...\CVS

...................................\.........\...\verilog

...................................\.........\...\.......\CVS

...................................\.........\...\.......\...\Entries

...................................\.........\...\.......\usbf_crc16.v

...................................\.........\...\.......\usbf_crc5.v

...................................\.........\...\.......\usbf_defines.v

...................................\.........\...\.......\usbf_ep_rf.v

...................................\.........\...\.......\usbf_ep_rf_dummy.v

...................................\.........\...\.......\usbf_idma.v

...................................\.........\...\.......\usbf_mem_arb.v

...................................\.........\...\.......\usbf_pa.v

...................................\.........\...\.......\usbf_pd.v

...................................\.........\...\.......\usbf_pe.v

...................................\.........\...\.......\usbf_pl.v

...................................\.........\...\.......\usbf_rf.v

...................................\.........\...\.......\usbf_top.v

...................................\.........\...\.......\usbf_utmi_if.v

...................................\.........\...\.......\usbf_utmi_ls.v

...................................\.........\...\.......\usbf_wb.v

...................................\.........\sim

...................................\.........\...\CVS

...................................\.........\...\rtl_sim

...................................\.........\...\.......\bin

...................................\.........\...\.......\...\CVS

...................................\.........\...\.......\CVS

...................................\.........\...\.......\run

...................................\.........\...\.......\...\CVS

...................................\.........\syn

...................................\.........\...\bin

...................................\.........\...\...\comp.dc

...................................\.........\...\...\CVS

...................................\.........\...\...\design_spec.dc

...................................\.........\...\...\lib_spec.dc

...................................\.........\...\...\read.dc

...................................\.........\...\CVS

...................................\.........\...\log

...................................\.........\...\...\CVS

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