一篇讲述计算PLL的环路滤波器的好文章

An Analysis and Performance Evaluation of a Passive Filter Design Technique for ChargeAn Analysis and Performance Evaluation of a Passive Filter Design Technique for Charge Pump PLL’s

An Analysis and Performance Evaluation of a Passive Filter Design Technique for Charge Pump PLL’s
The high performance of today’s digital phase-lock loop makes it the preferred choice for generation of stable, low noise, tunable local oscillators in wireless communications applications. This paper investigates the design of passive loop filters for Frequency Synthesizers utilizing a PhaseFrequency Detector and a current switch charge pump such as National Semiconductor’s PLLatinum Series. Passive filter design for a TYPE II third order phase-lock loop is discussed in depth, with some discussion of higher order filters included. Specific test results are presented for a GSM synthesizer design.