资料介绍
IC Design Flow - MarkDigital IC Design Flow Demo Design Information
Standard cells: 20K gate Memory blocks: RAM128x16, RAM256x16, ROM512x16 Analog block: PLL System clock frequency: 166MHz Process: TSMC 0.13m Low-K 7 Layer Metal Scan chains: 2
1
Deign Flow Overview
NC-Verilog RTL Simulation Pre-Layout Functional Verification
RTL Compiler
Synthesis
Logic Synthesis
Nano Encounter
Place & Route
Physical Implementation Post-Layout Functional Verification
NC-Verilog
Gate-Level Simulation
Conformal ASIC
Equivalence Check
Formal Verification
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RTL Simulation
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