资料介绍
RTL Design Style Guide for Verilog - V1Chapter 2 RTL Description Techniques
Chapter 2 RTL Description Techniques
This chapter introduces the basic style of RTL description using Verilog-HDL. In addition, it discusses items of which to take note when coding and provides some example codes. Performance of the synthesized circuits and the readability of the source code can be improved by following the description style and cautionary items introduced in this chapter.
Contents
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
Combinational logic always construct description in combinational logic FF inference Latch inference Tri-state buffer always construct description that takes circuit structure into account if statements
case statements for statements 2.10 Operator descriptions 2.11 State machine descriptions
2-1
2.1. Combinational