资料介绍
RTL Design Style Guide for Verilog - V1Chapter 1 Basic Design Constraints
Chapter 1 Basic Design Constraints
This chapter introduces naming conventions and synchronous design issues that should be kept in mind during the design process, as well as considerations and cautions relating to asynchronous design, clocks, and hierarchical design.
1.1 Naming conventions
Contents
1.2 Synchronous design 1.3 Initial reset 1.4 Clocks 1.5 Handling of asynchronous circuits 1.6 Hierarchical design
1-1
1.1. Naming Conventions
1.1. Naming conventions
1.1.1. Basic naming conventions
[1] [2] [3] [4] [5] [6] [7] [8] [9] File names should be as follows: ”.v” Only alphanumeric characters and the underscore ’_’ should be used, and the first character should be a letter of the alphabet Key words in Verilog-HDL(IEEE1364), VHDL(IEE
我要上传