资料介绍
DDR PRELIMINARY DATA SHEET
1G bits DDR2 SDRAM
EDE1108AEBG (128M words × 8 bits)
EDE1116AEBG (64M words × 16 bits)
Specifications Features
Density: 1G bits Double-data-rate architecture; two data transfers per
Organization clock cycle
16M words × 8 bits × 8 banks (EDE1108AEBG) The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
8M words × 16 bits × 8 banks (EDE1116AEBG)
Bi-directional differential data stro
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