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硬件乐曲自动演奏FPGA 开发板 DIY author :zhrscut
/*--------------------------------------------------------
-- Engineer: zhrscut
-- Create Date:
-- Module Name:
-- Tool Versions: Quartus_II 9.1
-- 欢迎加入 EEPW ，FPGA 开发板 DIY 活动
--------------------------------------------------------*/
module auto_piano(clk,beep);
input clk;
output beep;
reg beep_r;
reg[7:0] state;
reg[15:0] count,freq;
reg[23:0] counter;
//-----------------------------------
//¨
parameterM_1=16'd47774,
M_2=16'd42568,
M_3=16'd37919,
M_4=16'd35791,
M_5=16'd31888,
M_6=16'd28409,
M_7=16'd25309,
L_5=16'd63775;
//¤±
parameter timer=1250_0000;
//-----------------------------------
always @(posedge clk)
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