时钟发生器或合成的抖动测量

摘要：时钟（CLK）发生器和合成形成一个复杂的数字系统，并在时钟的信号质量错误的脉搏，可以有广泛的影响。

Maxim > App Notes > High-Speed Interconnect
Keywords: jitter, CLK generator, CLK synthesizer, clock jitter, cycle-to-cycle jitter, clock generators, synthesizers Sep 26, 2003

APPLICATION NOTE 2744
Jitter Measurements for CLK Generators or Synthesizers


Abstract:Clock (CLK) generators and synthesizers form the pulse of a complex digital system and errors in a clock's signal
quality can have wide-ranging effect.

One of the most important performance measurements is clock jitter. Jitter is defined as "the short-term variation of a signal with
respect to its ideal position in time." In a clock generator chip, there are many factors which contribute to output clock jitter, such
as the device noise, supply variation, jitter in the reference clock, loading condition, and interference