【应用笔记】AN531:使用硬件加速器降低功耗(AN 531: Reducing Power with Hardware Accelerators)

【应用笔记】AN531:使用硬件加速器降低功耗(AN 531: Reducing Power with Hardware Accelerators)
在使用FPGA的嵌入式产品中降低功耗越来越重要，特别是对于电池供电的应用、减少发热或成本等。
Reducing power consumption in embedded products that use FPGAs is
increasingly important, particularly for battery-powered applications or
to reduce heat or cost. You can use parallel algorithms to exploit the
parallel architecture of FPGA devices to accomplish more work per clock
cycle, allowing you to lower the clock frequency. High-level development
tools such as SOPC Builder and the Nios® II C-to-Hardware Acceleration
Compiler (C2H) can help you use the power-saving potential of the FPGA
hardware by easily adding hardware accelerators and lowering clock
frequencies.
AN 531: Reducing Power
with Hardware Accelerators

May 2008, ver. 1.0 Application Note 531



Introduction Reducing power consumption in embedded products that use FPGAs is
increasingly important, particularly for battery-powered applications or
to reduce heat or cost. You can use parallel algorithms to exploit the
parallel architecture of FPGA devices to accomplish more work per clock
cycle, allowing you to lower the clock frequency. High-level development
tools such as SOPC Builder and the Nios II C-to-Hardware Acceleration