【应用笔记】Altera器件的IEEE1149.1 JTAG边界扫描测试(IEEE 1149.1 JTAG Boundary-Scan Testing in Altera Devices)

【应用笔记】Altera器件的IEEE1149.1 JTAG边界扫描测试(IEEE 1149.1 JTAG Boundary-Scan Testing in Altera Devices)
当印刷电路板(PCB)变得越来越复杂的时候，全面彻底测试的需求也变得越来越重要呀。
As printed circuit boards (PCBs) become more complex, the need for
thorough testing becomes increasingly important. Advances in surfacemount
packaging and PCB manufacturing have resulted in smaller
boards, making traditional test methods—external test probes and “bedof-
nails” test fixtures—harder to implement. As a result, cost savings from
PCB space reductions are sometimes offset by cost increases in traditional
testing methods.
IEEE 1149.1 JTAG

Boundary-Scan Testing
in Altera Devices
June 2005, ver. 6.0 Application Note 39




Introduction As printed circuit boards (PCBs) become more complex, the need for
thorough testing becomes increasingly important. Advances in surface-
mount packaging and PCB manufacturing have resulted in smaller
boards, making traditional test methods―external test probes and “bed-