【应用笔记】AN367:在Stratix II器件中实现PLL重配置(AN 367: Implementing PLL Reconfiguration in Stratix II Devices)

【应用笔记】AN367:在Stratix II器件中实现PLL重配置(AN 367: Implementing PLL Reconfiguration in Stratix II Devices)
锁相环(Phase-locked loops,PLLs)使用几个分频计数器和不同的压控振荡器(voltage-controlled oscillator,VCO)相位节拍，来实现频率综合和相移。
Phase-locked loops (PLLs) use several divide counters and different
voltage-controlled oscillator (VCO) phase taps to perform frequency synthesis and
phase shifts. In Stratix® II enhanced and fast PLLs, you can reconfigure both the
counter settings and phaseshift the PLL output clock in real time. You can also change
the charge pump and loop filter components, which dynamically affects the PLL
bandwidth. You can use these PLL components to update the output clock frequency,
PLL bandwidth, and phaseshift in real time, without reconfiguring the entire FPGA.
AN 367: Implementing PLL
Reconfiguration in Stratix II Devices

May 2009 AN-367-2.1




Introduction
Phase-locked loops (PLLs) use several divide counters and different
voltage-controlled oscillator (VCO) phase taps to perform frequency synthesis and
phase shifts. In Stratix II enhanced and fast PLLs, you can reconfigure both the
counter settings and phaseshift the PLL output clock in real time. You can also change
the charge pump and loop f