【应用笔记】Cyclone II的DDR2 SDRAM示例(Cyclone II DDR2 SDRAM Demonstration)

【应用笔记】Cyclone II的DDR2 SDRAM示例(Cyclone II DDR2 SDRAM Demonstration)
本应用笔记描述了一个在Altera的Cyclone II EP2C35 DSP开发板上实现167MHz DDR2 SDRAM的示例。
This application note describes a 167-MHz DDR2 SDRAM demonstration
on an Altera® Cyclone™ II EP2C35 DSP Development Board.
The Altera Cyclone II EP2C35 DSP development board provides a lowcost
hardware platform for developing high performance DSP designs
based on Altera Cyclone II FPGA devices and interfaces to a DDR2
SDRAM. This application note describes how to run a pregenerated
Quartus® II project that demonstrates a DDR2 SDRAM interface
operating at 167 MHz. This application note also details how to modify
the demonstration project, and how the demonstration was created so
you can create a custom DDR2 interface.
Cyclone II DDR2 SDRAM
Demonstration

April 2005, ver 1.0 Application Note 383



Introduction This application note describes a 167-MHz DDR2 SDRAM demonstration
on an Altera Cyclone II EP2C35 DSP Development Board.

The Altera Cyclone II EP2C35 DSP development board provides a low-
cost hardware platform for developing high performance DSP designs
based on Altera Cyclone II FPGA devices and interfaces to a DDR2
SDRAM. This application note describes how to run a pregenerated