【应用笔记】理解Stratix II器件的PLL时序(Understanding PLL Timing for Stratix II Devices)

【应用笔记】理解Stratix II器件的PLL时序(Understanding PLL Timing for Stratix II Devices)
Stratix II器件有多达12个的PLL，可以为片上时钟管理、外部系统时钟管理以及高速I/O接口，提供强健的时钟管理和综合。
Stratix® II devices have up to 12 phase-locked loops (PLLs) that provide
robust clock management and synthesis for on-chip clock management,
external system clock management, and high-speed I/O interfaces. The
Stratix II PLL is highly versatile and can be used as a zero delay buffer,
jitter attenuator, low skew fan-out buffer, and as a frequency synthesizer.
To take advantage of the numerous features and capabilities provided by
the Stratix II PLLs, a full understanding of all reports and analysis
performed by the Quartus® II Timing Analyzer is necessary. This
application note provides details, examples, and guidelines on how to
read and understand the various Timing Analysis reports relating to
PLLs, and how the analysis is performed by the Timing Analyzer.
This application note is applicable to designs that target Stratix II devices
using the Quartus II software version 5.1 and earlier.
Understanding PLL Timing
for Stratix II Devices

March 2006, ver. 1.0 Application Note 411



Introduction Stratix II devices have up to 12 phase-locked loops (PLLs) that provide
robust clock management and synthesis for on-chip clock management,
external system clock management, and high-speed I/O interfaces. The
Stratix II PLL is highly versatile and can be used as a zero delay buffer,
jitter attenuator, low skew fan-out buffer, and as a frequency synthesizer.
To take advantage of the numerous