【应用笔记】AN461:在Stratix III和Stratix IV器件中实现QDRII+和QDRII SRAM接口设计指南(AN 461: Design Guidelines for Implementing QDRII+ and QDRII SRAM Interfaces in Stratix III and Stratix IV Devices)

【应用笔记】AN461:在Stratix III和Stratix IV器件中实现QDRII+和QDRII SRAM接口设计指南(AN 461: Design Guidelines for Implementing QDRII+ and QDRII SRAM Interfaces in Stratix III and Stratix IV Devices)
QDRII+ and the QDRII SRAM devices are ideally suited for bandwidth– intensive
and low-latency applications such as controller buffer memory, look-up tables (LUTs),
and linked lists. QDRII+ and QDRII SRAM memory architecture features separate
read and write ports operating twice per clock cycle to deliver a total of four data
transfers per cycle.
AN 461: Design Guidelines for Implementing
QDRII+ and QDRII SRAM Interfaces in Stratix III
and Stratix IV Devices

February 2010, v1.2




QDRII+ and the QDRII SRAM devices are ideally suited for bandwidth