【应用笔记】Stratix II GX同步开关噪声(SSN)设计指南(Stratix II GX SSN Design Guidelines)

【应用笔记】Stratix II GX同步开关噪声(SSN)设计指南(Stratix II GX SSN Design Guidelines)
如今的FPGA器件显示出亚微毫秒边沿速率来满足苛刻的时序要求，这些要求包括运行高速存储器接口、高速串行连接通信等。快速边沿速率的下降沿和大量并行I/O总线(DDR)耦合在一起，可以引起多种信号完整性问题，如串扰(包括同步开关噪声(SSN))。这些都可以导致系统性能下降，如果在初始设计阶段不考虑这些问题的的话。这遍应用笔记对同步开关噪声，以及降低在Stratix II GX系列器件中所观察到的噪声不同技巧等的主要机制提供了一些信息。
Today's FPGA devices exhibit sub-nanosecond edge rates to meet the
critical timing requirements needed to run high-speed memory
interfaces, and communicate over high-speed serial links. The downside
of fast edge rates coupled with large parallel I/O buses (DDR) can cause
a variety of signal integrity problems like crosstalk, including
simultaneous switching noise (SSN), which can result in degradation of
system performance if it is not accounted for during the initial design
phase.
This application note provides information on the major mechanisms of
simultaneous switching noise, along with various techniques to mitigate
the observed noise in the Stratix® II GX device family. In addition, this
application note explains how Altera® defines signal margin, covers the
impact of multiple I/Os toggling on transceiver performance, and
concludes by providing a high-level overview of best practices for
designing a board.
Stratix II GX SSN Design
Guidelines

August 2007, ver. 1.0 Application Note 472



Introduction Today's FPGA devices exhibit sub-nanosecond edge rates to meet the
critical timing requirements needed to run high-speed memory
interfaces, and communicate over high-speed serial links. The downside
of fast edge rates coupled with large parallel I/O buses (DDR) can cause
a variety of signal integrity problems like crosstalk, including
simultaneous switching noise (SSN), which can result in