将 DDR SDRAM 与 CoolRunner-II CPLD 接口

将 DDR SDRAM 与 CoolRunner-II CPLD 接口
Application Note: CoolRunner-II CPLDs

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Interfacing to DDR SDRAM with
CoolRunner-II CPLDs
XAPP384 (v1.0) Febuary 14, 2003


Summary This document describes a reference design for interfacing CoolRunner-II CPLDs with
double data rate (DDR) SDRAM memory devices. The built reference design is capable of
100 MHz operation. The VHDL code described here can be found in VHDL Code, page 19.




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