资料介绍
参考系统:带有 OPB 中心 DMA 的 PLB DDR2 Application Note: Embedded Processing
R Reference System: PLB DDR2 with
OPB Central DMA
XAPP935 (v1.1) June 7, 2007 Author: James Lucero
Abstract This reference system demonstrates the functionality of the Processor Local Bus (PLB) Double
Data Rate 2 (DDR2) Synchronous DRAM (SDRAM) memory controller in a PowerPC 405
(PPC) 405 processor system. The On-Chip Peripheral Bus (OPB) Central DMA controller is