【应用手册】AN 571: Implementing the SERDES Framer Interface Level 5 (SFI-5.1) Protocol in Stratix IV Devices

【应用手册】AN 571: Implementing the SERDES Framer Interface Level 5 (SFI-5.1) Protocol in Stratix IV Devices
This application note describes how to implement an SFI-5.1 interface using Altera’s
40 nm Stratix® IV GX and Stratix IV GT devices.
The SFI-5.1 is a chip-to-chip or chip-to-module protocol that targets 40 Gbps
applications. The protocol allows up to 25% overhead for forward error correction
(FEC) code for a maximum throughput of 50 Gbps.
Both Stratix IV GX and Stratix IV GT devices support SFI-5.1 interfaces using
high-speed CDR-based transceivers.
Figure 1 shows a typical OC-768 packet over SONET (POS) line card application that
uses a Stratix IV GX device to implement an OC-768 framer and FEC processor. The
line-side interface to the 40G optical module uses SFI-5.1, while the system-side
interface to the packet processor uses either the industry-standard Interlaken or the
proprietary SerialLite II protocol.
AN 571: Implementing the SERDES Framer
Interface Level 5 (SFI-5.1) Protocol in
Stratix IV Devices
AN-571-1.1 Application Note




Introduction
This application note describes how to implement an SFI-5.1 interface using Altera’s
40 nm Stratix IV GX and Stratix IV GT devices.
The SFI-5.1 is a chip-to-chip or chip-to-module protocol that targets 40 Gbps