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【应用手册】Dynamic Reconfiguration of Transceiver Channels Using Multiple PLLs in Stratix IV Devices

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【应用手册】Dynamic Reconfiguration of Transceiver Channels Using Multiple PLLs in Stratix IV Devices
This application note describes how you can dynamically reconfigure your Stratix® IV
transceiver channels using the multiple phase-locked loop (PLL) dynamic
reconfiguration feature. This feature allows you to reconfigure a transceiver channel
to switch among PLLs (CMU PLLs) within the transceiver block and the PLLs (CMU
and [auxiliary transmit] ATX PLLs) located outside the transceiver block. Using this
feature, you can independently switch a transceiver channel to at least four
independent and distinct data rates typically required by universal front end (UFE)
applications.
■ The CMU PLL-based dynamic reconfiguration feature allows you to reconfigure
the transmitter side of a transceiver channel independently by either switching to
one of the two clock multiplier unit PLLs (CMU PLLs) within the transceiver block
or by reconfiguring a CMU PLL to the data rate you require. However, with this
CMU PLL reconfiguration approach, the other channels within the transceiver
block listening to the same CMU PLL are also affected. Dynamically reconfiguring
using multiple PLLs overcomes this issue.
■ The focus of this application note is about reconfiguring the transmitter side of the
transceiver channel. Because each receiver channel has a dedicated clock and data
recovery (CDR) that can be reconfigured to any supported data rate, the
reconfiguration of the receiver side is not affected by any PLL resource.
Dynamic Reconfiguration of Transceiver
Channels Using Multiple PLLs in Stratix IV
Dynamic Reconfiguration of Transceiver
Channels Using Multiple PLLs in Stratix IV Devices
AN-607-1.2 Application Note




This application note describes how you can dynamically reconfigure your Stratix IV
transceiver channels using the multiple phase-locked loop (PLL) dynamic
reconfiguration featur……
【应用手册】Dynamic Reconfiguration of Transceiver Channels Using Multiple PLLs in Stratix IV Devices
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