数字锁相环 (DPLL) 参考设计

数字锁相环 (DPLL) 参考设计
Application Note: Virtex-4 FPGAs

R Digital Phase-Locked Loop (DPLL)
Reference Design
XAPP854 (v1.0) October 10, 2006 Author: Justin Gaither



Summary Many applications require a clock signal to be synchronous, phase-locked, or derived from
another signal, such as a data signal or another clock. This type of clock circuit is important in
many communications or audio video applications to keep data synchronize