【应用手册】Sharing External Memory Bandwidth Using the Multi-Port Front-End Reference Design

【应用手册】Sharing External Memory Bandwidth Using the Multi-Port Front-End Reference Design
This document describes the features and architecture of the Altera® Multi-Port
Front-End (MPFE) reference design, details the design flow you should follow to
integrate the MPFE block into your design, and illustrates the functionality of the
MPFE block in an example system with multiple masters.
The MPFE reference design allows you to efficiently share access to external memory
between multiple data masters in your design. Combined with the Altera DDR2 and
DDR3 SDRAM Controller with UniPHY, the MPFE block allows efficient access to
DDR2 or DDR3 SDRAM memories.
In this document, the terms master and slave are relative to the MPFE reference
design, unless specifically referred to as a master in your system. The master port on
the MPFE block connects to the slave port on the memory controller. Each slave port
on the MPFE connects to the master port on the user logic block in your system that
requires access to external memory.
Sharing External Memory Bandwidth
Using the Multi-Port Front-End Reference
Design
AN-637-01 Application Note




This document describes the features and architecture of the Altera Multi-Port
Front-End (MPFE) reference design, details the design flow you should follow to
integrate the MPFE block into your design, and illustrates the functionality of the