【应用手册】Test Methodology of Error Detection and Recovery using CRC in Altera FPGA Devices

【应用手册】Test Methodology of Error Detection and Recovery using CRC in Altera FPGA Devices
This application note describes how to use the enhanced error detection cyclic
redundancy check (CRC) feature in the Arria II, Stratix III, Stratix IV, Stratix V, and
later devices. It also describes the test methodology you can use when testing the
capability of this feature in the supported devices. Stratix V and later devices also
support error correction feature.
During FPGA configuration, the error detection CRC feature detects configuration
bitstream corruption when the bitstream is transferred from an external device into
the FPGA. In user mode, the error detection CRC feature detects a single event upset
(SEU) and determines the error type and location. In addition, Stratix V and later
devices support internal scrubbing, an ability to correct errors detected in user mode.
Test Methodology of Error Detection and
Recovery using CRC in Altera FPGA
Devices
AN-539-2.0 Application Note




This application note describes how to use the enhanced error detection cyclic
redundancy check (CRC) feature in the Arria II, Stratix III, Stratix IV, Stratix V, and
later devices. It also describes the test methodology you can